T. Inoue, Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Fujiwara, Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Michinishi, Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
T. Yokohira, Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
T. Okamoto, Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.
Index Terms:
field programmable gate arrays; fault diagnosis; logic testing; table lookup; automatic test software; logic CAD; design for testability; computational complexity; field-programmable gate array; universal test complexity; arbitrary logic circuits; look-up tables; sequential loading; random access loading; programming schemes; block-sliced loading; C-testable; configuration memory cells; fault model
Citation:
T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, T. Okamoto, "Universal test complexity of field-programmable gate arrays," ats, pp.259, Fourth Asian Test Symposium (ATS'95), 1995