A parallel sequential test generation system DESCARTES based on real-valued logic simulation

A
ATS
1995
Fourth Asian Test Symposium (ATS'95)
Abstract - A parallel sequential test generation system DESCARTES based on real-valued logic simulation

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Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	H. Date, M. Nakao, K. Hatayama, "A parallel sequential test generation system DESCARTES based on real-valued logic simulation," Asian Test Symposium, pp. 252, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485344, author = {H. Date and M. Nakao and K. Hatayama}, title = {A parallel sequential test generation system DESCARTES based on real-valued logic simulation}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {252}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485344}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A parallel sequential test generation system DESCARTES based on real-valued logic simulation SN - 0-8186-7129-7 SP EP A1 - H. Date, A1 - M. Nakao, A1 - K. Hatayama, PY - 1995 KW - logic testing; sequential circuits; fault diagnosis; logic CAD; parallel algorithms; computational complexity; redundancy; automatic test software; VLSI; design for testability; parallel sequential test generation system; DESCARTES; real-valued logic simulation; synchronous sequential circuits; automatic test generation; redundant fault identification program; algorithmic test generation program; test quality; ISCAS '89 benchmark sequential circuits; VLSI design; stuck-at faults; distributed processing environment oriented system; concurrent accelerative test generation VL - 0 JA - Asian Test Symposium ER -

H. Date, Res. Lab., Hitachi Ltd., Ibaraki, Japan

M. Nakao, Res. Lab., Hitachi Ltd., Ibaraki, Japan

K. Hatayama, Res. Lab., Hitachi Ltd., Ibaraki, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485344

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach.

Index Terms:

logic testing; sequential circuits; fault diagnosis; logic CAD; parallel algorithms; computational complexity; redundancy; automatic test software; VLSI; design for testability; parallel sequential test generation system; DESCARTES; real-valued logic simulation; synchronous sequential circuits; automatic test generation; redundant fault identification program; algorithmic test generation program; test quality; ISCAS '89 benchmark sequential circuits; VLSI design; stuck-at faults; distributed processing environment oriented system; concurrent accelerative test generation

Citation:

H. Date, M. Nakao, K. Hatayama, "A parallel sequential test generation system DESCARTES based on real-valued logic simulation," ats, pp.252, Fourth Asian Test Symposium (ATS'95), 1995

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