Identification of robust untestable path delay faults

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	Similar Articles Articles by Wen Ching Wu Articles by Chung Len Lee Articles by J.E. Chen

Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	Wen Ching Wu, Chung Len Lee, J.E. Chen, "Identification of robust untestable path delay faults," Asian Test Symposium, pp. 229, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485341, author = {Wen Ching Wu and Chung Len Lee and J.E. Chen}, title = {Identification of robust untestable path delay faults}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {229}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485341}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Identification of robust untestable path delay faults SN - 0-8186-7129-7 SP EP A1 - Wen Ching Wu, A1 - Chung Len Lee, A1 - J.E. Chen, PY - 1995 KW - combinational circuits; fault diagnosis; logic testing; automatic testing; delays; logic partitioning; multivalued logic; signal flow graphs; logic CAD; robust untestable path delay faults; fault identification; path reconvergence of fanouts; ISCAS 85' circuits; total path delay faults; ATPG; combinational circuits; six-valued logic; propagation graph; ROUNTEST program; partitioning VL - 0 JA - Asian Test Symposium ER -

Wen Ching Wu, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

J.E. Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485341

This paper presents a theoretical analysis to identify robust untestable path delay faults. It first classifies the path reconvergence of fanouts into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure was applied to ISCAS 85' circuits and it was found that the robust untestable faults occupy a high percentage of the total path delay faults. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit.

Index Terms:

combinational circuits; fault diagnosis; logic testing; automatic testing; delays; logic partitioning; multivalued logic; signal flow graphs; logic CAD; robust untestable path delay faults; fault identification; path reconvergence of fanouts; ISCAS 85' circuits; total path delay faults; ATPG; combinational circuits; six-valued logic; propagation graph; ROUNTEST program; partitioning

Citation:

Wen Ching Wu, Chung Len Lee, J.E. Chen, "Identification of robust untestable path delay faults," ats, pp.229, Fourth Asian Test Symposium (ATS'95), 1995

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