Characterization of a special class of nongroup CA termed as D1*CA has been proposed previously (1993) along with its application for synthesis of easily testable FSM. This paper extends application of the D1*CA as an ideal test machine for testing combinational logic (CL) blocks and registers of a circuit. Such a test machine can be conveniently embedded in the data path synthesis phase around the function realized by a CL block and the register feeding the input data to the CL. In the normal mode of operation, the register and the CL realize the intended function. During testing, the D1*CA runs in autonomous mode generating the test vectors and also accumulating test responses. It is sufficient to observe the response only from the leftmost CA cell with aliasing error probability approaching zero value. Experiments conducted on CL benchmarks confirm 100% fault coverage of all stuck-at faults in CL and its associated lines. It does not incur any test generation and test application overheads. Further, test parallelism can be achieved through simultaneous testing of multiple combinational modules in a chip. The scheme provides a cost effective alternative to scan path.