M. Renovell, Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
F. Azais, Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand, Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method.
Index Terms:
design for testability; mixed analogue-digital integrated circuits; integrated circuit testing; controllability; observability; production testing; design-for-test technique; multistage analog circuits; mixed-signal circuits; DFT approach; op-amp-based modules; testability resources; controllability; observability; transparent paths; external I/O; local I/O; test mode; on-chip digital resources; analog response penalty; test management
Citation:
M. Renovell, F. Azais, Y. Bertrand, "A design-for-test technique for multistage analog circuits," ats, pp.113, Fourth Asian Test Symposium (ATS'95), 1995