Chen-Pin Kung, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Shang Lin, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propagation methods are incorporated into BISTSIM. The experimental results show that the proposed fault simulator delivers better performance than FSIM; about 2 to 3 times for circuits with a large number of test patterns. For signature evaluation of MISR to determine the aliasing, two efficient simulation methods, bit-array computation and parallel-pattern sequential simulation, are proposed. The resultant BISTSIM outperforms the fast fault simulator HOPE1.1 with an average speedup ratio of 10.
Index Terms:
built-in self test; combinational circuits; logic testing; digital simulation; circuit analysis computing; VLSI; integrated circuit testing; signature computation; BIST applications; combinational fault simulation; test patterns; BISTSIM; demand-driven logic simulation algorithm; fault propagation methods; MISR; aliasing; bit-array computation; parallel-pattern sequential simulation; speedup ratio; VLSI
Citation:
Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin, "Fast fault simulation for BIST applications," ats, pp.93, Fourth Asian Test Symposium (ATS'95), 1995
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