Overhead reduction techniques for hierarchical fault simulation are presented which reduce simulation overhead for the concurrent method and its expanded version, the Multi-List-Traversal method. The techniques include a one-pass fault simulation strategy, characteristic vectors, and contiguous concurrent machines. The cost of each process for the conventional and new methods is formulated for comparison. The methods were implemented in C, and experiments were conducted using ISCAS benchmark circuits. The results show that the new techniques make conventional concurrent fault simulators up to 4.9 times faster and also that the performance can be improved by fault ordering.
Index Terms:
combinational circuits; fault diagnosis; logic testing; ULSI; circuit analysis computing; digital simulation; concurrent engineering; logic CAD; multivalued logic circuits; overhead reduction techniques; hierarchical fault simulation; simulation overhead; concurrent method; multi-list-traversal method; one-pass fault simulation strategy; characteristic vectors; contiguous concurrent machines; ISCAS benchmark circuits; fault ordering; ULSI; logic test sequences
Citation:
E. Harada, J.H. Patel, "Overhead reduction techniques for hierarchical fault simulation," ats, pp.79, Fourth Asian Test Symposium (ATS'95), 1995
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