A simple technique for locating gate-level faults in combinational circuits

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Fourth Asian Test Symposium (ATS'95)

Bangalore, India

November 23-November 24

ISBN: 0-8186-7129-7

	ASCII Text	x
	T. Yamada, K. Yamazaki, E.J. McCluskey, "A simple technique for locating gate-level faults in combinational circuits," Asian Test Symposium, pp. 65, Fourth Asian Test Symposium (ATS'95), 1995.

	BibTex	x
	@article{ 10.1109/ATS.1995.485318, author = {T. Yamada and K. Yamazaki and E.J. McCluskey}, title = {A simple technique for locating gate-level faults in combinational circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1995}, isbn = {0-8186-7129-7}, pages = {65}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485318}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - A simple technique for locating gate-level faults in combinational circuits SN - 0-8186-7129-7 SP EP A1 - T. Yamada, A1 - K. Yamazaki, A1 - E.J. McCluskey, PY - 1995 KW - combinational circuits; fault diagnosis; logic testing; computational complexity; VLSI; integrated circuit testing; scanning electron microscopy; electron probe analysis; optical microscopy; circuit analysis computing; digital simulation; gate-level faults; combinational circuits; error sources; fault deduction; fault elimination; ISCAS'85 benchmark circuits; computation time; diagnostic resolution; physical defect analysis; scanning electron microscopy; electron beam probing; light emission microscopy; VLSI VL - 0 JA - Asian Test Symposium ER -

T. Yamada, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

K. Yamazaki, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

E.J. McCluskey, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485318

This paper presents a simple technique for locating single gate-level faults in combinational circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to evaluate its performance. The computation time is very short while a high diagnostic resolution may not always be guaranteed. Therefore this would be useful as a preprocess for analyzing the physical defect by various tools such as scanning electron microscopy, electron beam probing and light emission microscopy.

Index Terms:

combinational circuits; fault diagnosis; logic testing; computational complexity; VLSI; integrated circuit testing; scanning electron microscopy; electron probe analysis; optical microscopy; circuit analysis computing; digital simulation; gate-level faults; combinational circuits; error sources; fault deduction; fault elimination; ISCAS'85 benchmark circuits; computation time; diagnostic resolution; physical defect analysis; scanning electron microscopy; electron beam probing; light emission microscopy; VLSI

Citation:

T. Yamada, K. Yamazaki, E.J. McCluskey, "A simple technique for locating gate-level faults in combinational circuits," ats, pp.65, Fourth Asian Test Symposium (ATS'95), 1995

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