This paper suggests an experimental method for determining metastability properties based on deliberately inducing metastability in edge-triggered flip-flops. It offers the opportunity to analyze the impact of input signals time relationship on the output signal timing characteristics, using graphical and analytical representation of the propagation delay density distribution function. A new approach for counting the number of fault events, using the integrated propagation delay density distribution function is proposed. From the measured results, the flip-flop normal propagation delay and the resolution time constant are determined. Using the time search approach in provoking metastable behavior enables an accurate and repeatable statistical measurement, as well as automatic data acquisition of the Mean Time Between Failures (MTBF) characteristic. The method is applicable to a wide range of semiconductor flip-flops and latch devices, from discrete to more sophisticated LSI and VLSI technologies as: custom CMOS, ASIC, PLD. The results might be helpful in the design and testing of asynchronous combinatorial and sequential logic, as well as of complex architecture microsystems with a high clock frequencies.