This paper presents the circuit design for phase alignment in a Digital Frequency Synthesizer (DFS), taking advantage of asynchronous level-mode state machines. An example of a real case asynchronous design is presented that provides superior results to alternative solutions. The designs are implemented in the Xilinx Spartan™-III family, a field programmable device in the 90nm technology. We explain the specific clock management application and the circuits for our designs, followed by a summary of the final results. Our silicon results indicate functionality improvement, area decrease, and jitter reduction compared to alternatives. In addition, taking advantage of novel asynchronous circuits saves engineering effort during silicon characterization and design of future generations of products.