High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases where the producer and consumer clock rates differ, however, the issue of flow control has remained a problem. Compared to more traditional pointer FIFOs, the highly dynamic internal state of ripple FIFOs makes it difficult to estimate the instantaneous occupancy, or "fullness" of the FIFO. To prevent overflow, the sender must know when the FIFO is getting too full. To prevent underflow, the receiver must know when the FIFO is getting too empty. In this paper, we present a novel method for estimating ripple FIFO occupancy by detecting regions of local data congestion and data starvation. The solution is very simple and is suitable for use with many common FIFO protocols. The core idea involves the use of a phase comparator circuit to monitor the relative timing of control signals at FIFO stage boundaries.