Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits

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Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02)

Manchester, United Kingdom

April 08-April 11

ISBN: 0-7695-1540-1

	ASCII Text	x
	Metehan Özcan, Takashi Nanya, Masashi Imai, "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits," Asynchronous Circuits and Systems, International Symposium on, pp. 109, Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02), 2002.

	BibTex	x
	@article{ 10.1109/ASYNC.2002.1000301, author = {Metehan Özcan and Takashi Nanya and Masashi Imai}, title = {Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {2002}, issn = {1522-8681}, pages = {109}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2002.1000301}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits SN - 1522-8681 SP EP A1 - Metehan Özcan, A1 - Takashi Nanya, A1 - Masashi Imai, PY - 2002 KW - null VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Metehan Özcan, University of Tokyo

Takashi Nanya, University of Tokyo

Masashi Imai, University of Tokyo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2002.1000301

Timing analysis is a method for verification of timing constraints in a digital circuit. Asynchronous circuits bring new concerns for timing analysis with their local completion circuits, which generate cycles in the circuit and require special handling. In this paper, constraints in fine-grain pipelined asynchronous data-path circuits are examined in detail and a tool environment for automatic generation and verification of these constraints are presented along with some sample layout results.

Citation:

Metehan Özcan, Takashi Nanya, Masashi Imai, "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits," async, pp.109, Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02), 2002

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