A Low-Power Self-Timed Viterbi Decoder

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	Similar Articles Articles by P.A. Riocreux Articles by L.E.M. Brackenbury Articles by M. Cumpstey Articles by S.B. Furber

Seventh International Symposium on Asynchronous Circuits and Systems (ASYNC'01)

Salt Lake City, Utah

March 11-March 14

ISBN: 0-7695-1034-5

	ASCII Text	x
	P.A. Riocreux, L.E.M. Brackenbury, M. Cumpstey, S.B. Furber, "A Low-Power Self-Timed Viterbi Decoder," Asynchronous Circuits and Systems, International Symposium on, pp. 15, Seventh International Symposium on Asynchronous Circuits and Systems (ASYNC'01), 2001.

	BibTex	x
	@article{ 10.1109/ASYNC.2001.914065, author = {P.A. Riocreux and L.E.M. Brackenbury and M. Cumpstey and S.B. Furber}, title = {A Low-Power Self-Timed Viterbi Decoder}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {2001}, issn = {1522-8681}, pages = {15}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2001.914065}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - A Low-Power Self-Timed Viterbi Decoder SN - 1522-8681 SP EP A1 - P.A. Riocreux, A1 - L.E.M. Brackenbury, A1 - M. Cumpstey, A1 - S.B. Furber, PY - 2001 VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

P.A. Riocreux, University of Manchester

L.E.M. Brackenbury, University of Manchester

M. Cumpstey, University of Manchester

S.B. Furber, University of Manchester

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2001.914065

Viterbi decoders are used for decoding data encoded using convolutional forward error correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital TV broadcast, CD-ROM and magnetic disk reading. This paper describes a design for a self-timed Viterbi decoder. The new design is based upon serial, unary arithmetic for the manipulation and storage of metrics. In the trace-back system, multiple concurrent trace-backs may be running and trace-backs are terminated as soon as they cease to be useful. The new architecture occupies between 29% and 23% less area than a selection of synchronous implementations with the same design parameters which use the same process and cell-library.

Citation:

P.A. Riocreux, L.E.M. Brackenbury, M. Cumpstey, S.B. Furber, "A Low-Power Self-Timed Viterbi Decoder," async, pp.15, Seventh International Symposium on Asynchronous Circuits and Systems (ASYNC'01), 2001

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