This paper introduces several new asynchronous pipeline designs, which offer high throughput as well as low latency. The designs target dynamic datapaths, both dual-rail as well as single-rail. The new pipelines are latch-free and therefore are particularly well suited for fine-grain pipelining, i.e., where each pipeline stage is only a single gate deep. The pipelines employ new control structures and protocols aimed at reducing the handshaking delay, the principal impediment to achieving high throughput in asynchronous pipelines.As a test vehicle, a 4-bit FIFO was designed using 0.6-micron technology. The results of careful HSPICE simulations of the FIFO designs are very encouraging. The dual-rail designs deliver a throughput of up to 860 million data items per second. This performance represents an improvement by a factor of 2 over a widely used comparable approach by Williams. The new single-rail designs deliver a throughput of up to 1208 million data items per second.