The two-phase asynchronous wave-pipeline design style presented in this paper is targeted at VLSI systems operating at Giga rates where it is rather difficult and costly to maintain the synchronous paradigm. Its distinguishing properties are the use of a request signal only, simple latches and the inelastic wave-pipelined operation. The asynchronous wave-pipeline is found to have less overhead and to be more robust than the synchronous one. The same basic structure is suitable for both data and control. Buildings blocks of a distributed arithmetic-based 2D-DCT are shown. Simulations of circuits to be fabricated on a 0.6um CMOS process show throughput rates as high as 800$\,$MHz for the 2D-DCT.