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Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)
Memory Faults in Asynchronous Microprocessors
Barcelona, Spain
April 19-April 21
ISBN: 0-7695-0031-5
D.W. Lloyd, University of Manchester
J.D. Garside, University of Manchester
D.A. Gilbert, University of Manchester
Although a large number of asynchronous microprocessors have now been designed, relatively few have attempted to handle memory faults. Memory faults create problems for the design of any pipelined system which are exacerbated by the non-deterministic nature of an asynchronous processor.This paper describes these problems as encountered in the design of asynchronous ARM processors and discusses their specific solutions in the AMULET3 processor. Different mechanisms were used, as expedient, to maintain coherency for the various state-holding elements within the processor; these include register renaming and history buffering in addition to resource locking.
Citation:
D.W. Lloyd, J.D. Garside, D.A. Gilbert, "Memory Faults in Asynchronous Microprocessors," async, pp.71, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999
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