A Timing Verifier and Timing Profiler for Asynchronous Circuits

A
ASYNC
1999
Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)
Abstract - A Timing Verifier and Timing Profiler for Asynchronous Circuits

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Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99)

Barcelona, Spain

April 19-April 21

ISBN: 0-7695-0031-5

	ASCII Text	x
	Per Arne Karlsen, Per Torstein Røine, "A Timing Verifier and Timing Profiler for Asynchronous Circuits," Asynchronous Circuits and Systems, International Symposium on, pp. 13, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASYNC.1999.761519, author = {Per Arne Karlsen and Per Torstein Røine}, title = {A Timing Verifier and Timing Profiler for Asynchronous Circuits}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1999}, issn = {1522-8681}, pages = {13}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761519}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - A Timing Verifier and Timing Profiler for Asynchronous Circuits SN - 1522-8681 SP EP A1 - Per Arne Karlsen, A1 - Per Torstein Røine, PY - 1999 VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Per Arne Karlsen, University of Oslo

Per Torstein Røine, University of Oslo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761519

A system for timing verification and timing profiling of asynchronous circuits is presented. A hierarchical netlist is simulated with an ordinary simulator such as HSPICE. Signal transition information is extracted from the simulation results. The system uses this information and the netlist to compare the circuit to Generalized Signal Transition Graph specifications by simulating the flow of tokens in the graphs. If a signal makes a transition that is not allowed by the specification, a timing error has occurred. The flow of tokens in the graph is also used to produce timing statistics for the circuit. Based on these statistics, timing optimization can be done in an iterative design process.

Citation:

Per Arne Karlsen, Per Torstein Røine, "A Timing Verifier and Timing Profiler for Asynchronous Circuits," async, pp.13, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999

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