An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 1/2 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 $B&L (Bm triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45ns in the worst case.