Efficient Timing Analysis Algorithms for Timed State Space Exploration

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	Similar Articles Articles by Wendy Belluomini Articles by Chris J. Myers

Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97)

Eindhoven, THE NETHERLANDS

April 07-April 10

ISBN: 0-8186-7922-0

	ASCII Text	x
	Wendy Belluomini, Chris J. Myers, "Efficient Timing Analysis Algorithms for Timed State Space Exploration," Asynchronous Circuits and Systems, International Symposium on, pp. 88, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997.

	BibTex	x
	@article{ 10.1109/ASYNC.1997.587166, author = {Wendy Belluomini and Chris J. Myers}, title = {Efficient Timing Analysis Algorithms for Timed State Space Exploration}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1997}, isbn = {0-8186-7922-0}, pages = {88}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587166}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Efficient Timing Analysis Algorithms for Timed State Space Exploration SN - 0-8186-7922-0 SP EP A1 - Wendy Belluomini, A1 - Chris J. Myers, PY - 1997 KW - timing KW - timing analysis algorithms KW - timed state space exploration KW - timed circuit synthesis KW - asynchronous circuits KW - computational complexity KW - geometric regions KW - partial orders VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Wendy Belluomini, Computer Science Department, University of Utah, UT

Chris J. Myers, Electrical Engineering Department, University of Utah, UT

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587166

This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Much of the computational complexity in the synthesis of timed circuits currently is in finding the reachable timed state space. We introduce new algorithms which utilize geometric regions to represent the timed state space and partial orders to minimize the number of regions necessary. These algorithms operate on specifications sufficiently general to describe practical circuits.

Index Terms:

timing, timing analysis algorithms, timed state space exploration, timed circuit synthesis, asynchronous circuits, computational complexity, geometric regions, partial orders

Citation:

Wendy Belluomini, Chris J. Myers, "Efficient Timing Analysis Algorithms for Timed State Space Exploration," async, pp.88, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

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