Two-Phase Asynchronous Pipeline Control

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Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97)

Eindhoven, THE NETHERLANDS

April 07-April 10

ISBN: 0-8186-7922-0

	ASCII Text	x
	S.S. Appleton, S.V. Morton, M.J. Liebelt, "Two-Phase Asynchronous Pipeline Control," Asynchronous Circuits and Systems, International Symposium on, pp. 12, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997.

	BibTex	x
	@article{ 10.1109/ASYNC.1997.587140, author = {S.S. Appleton and S.V. Morton and M.J. Liebelt}, title = {Two-Phase Asynchronous Pipeline Control}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1997}, isbn = {0-8186-7922-0}, pages = {12}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587140}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Two-Phase Asynchronous Pipeline Control SN - 0-8186-7922-0 SP EP A1 - S.S. Appleton, A1 - S.V. Morton, A1 - M.J. Liebelt, PY - 1997 KW - microprocessor chips KW - two-phase asynchronous pipeline control KW - bounded-delay model KW - prototype microprocessor VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

S.S. Appleton, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

S.V. Morton, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

M.J. Liebelt, Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.1997.587140

In this paper the potential speed and power efficiency of two-phase asynchronous systems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented.

Index Terms:

microprocessor chips, two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor

Citation:

S.S. Appleton, S.V. Morton, M.J. Liebelt, "Two-Phase Asynchronous Pipeline Control," async, pp.12, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

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