Hades-towards the design of an asynchronous superscalar processor

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	Similar Articles Articles by C.J. Elston Articles by D.B. Christianson Articles by P.A. Findlay Articles by G.B. Steven

Second Working Conference on Asynchronous Design Methodologies

London, England

May 30-May 31

ISBN: 0-8186-7098-3

	ASCII Text	x
	C.J. Elston, D.B. Christianson, P.A. Findlay, G.B. Steven, "Hades-towards the design of an asynchronous superscalar processor," Asynchronous Circuits and Systems, International Symposium on, pp. 200, Second Working Conference on Asynchronous Design Methodologies, 1995.

	BibTex	x
	@article{ 10.1109/WCADM.1995.514657, author = {C.J. Elston and D.B. Christianson and P.A. Findlay and G.B. Steven}, title = {Hades-towards the design of an asynchronous superscalar processor}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7098-3}, pages = {200}, doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514657}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Hades-towards the design of an asynchronous superscalar processor SN - 0-8186-7098-3 SP EP A1 - C.J. Elston, A1 - D.B. Christianson, A1 - P.A. Findlay, A1 - G.B. Steven, PY - 1995 KW - computer architecture; logic design; asynchronous superscalar processor; Hades; generic processor architecture; asynchronous processor design; decoupled operand forwarding; register writeback VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

C.J. Elston, Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

D.B. Christianson, Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

P.A. Findlay, Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

G.B. Steven, Div. of Comput. Sci., Hertfordshire Univ., Hatfield, UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514657

This paper uses Hades, a generic processor architecture aimed at single and multiple-instruction-issue asynchronous implementations, to illustrate some of the difficulties encountered in asynchronous processor design. Particular emphasis is placed on a decoupled operand forwarding mechanism which allows the last result of each functional unit to be forwarded to following instructions, yet completely separates forwarding from the register writeback operation.

Index Terms:

computer architecture; logic design; asynchronous superscalar processor; Hades; generic processor architecture; asynchronous processor design; decoupled operand forwarding; register writeback

Citation:

C.J. Elston, D.B. Christianson, P.A. Findlay, G.B. Steven, "Hades-towards the design of an asynchronous superscalar processor," async, pp.200, Second Working Conference on Asynchronous Design Methodologies, 1995

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