Asynchronous circuits based on multiple localised current-sensing completion detection

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Second Working Conference on Asynchronous Design Methodologies

London, England

May 30-May 31

ISBN: 0-8186-7098-3

	ASCII Text	x
	E. Grass, S. Jones, "Asynchronous circuits based on multiple localised current-sensing completion detection," Asynchronous Circuits and Systems, International Symposium on, pp. 170, Second Working Conference on Asynchronous Design Methodologies, 1995.

	BibTex	x
	@article{ 10.1109/WCADM.1995.514654, author = {E. Grass and S. Jones}, title = {Asynchronous circuits based on multiple localised current-sensing completion detection}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7098-3}, pages = {170}, doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514654}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Asynchronous circuits based on multiple localised current-sensing completion detection SN - 0-8186-7098-3 SP EP A1 - E. Grass, A1 - S. Jones, PY - 1995 KW - asynchronous circuits; logic design; power consumption; asynchronous circuits; dual rail coding; Current-Sensing Completion Detection; parallel multiplier; granularity; Current-Sensing Circuits; BiCMOS VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

E. Grass, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK

S. Jones, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514654

Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC's) which fully support the advantages of CSCD are presented. Multiple localised CSC's are studied and an example of a 4-bit parallel multiplier is investigated on different levels of granularity.

Index Terms:

asynchronous circuits; logic design; power consumption; asynchronous circuits; dual rail coding; Current-Sensing Completion Detection; parallel multiplier; granularity; Current-Sensing Circuits; BiCMOS

Citation:

E. Grass, S. Jones, "Asynchronous circuits based on multiple localised current-sensing completion detection," async, pp.170, Second Working Conference on Asynchronous Design Methodologies, 1995

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