Among the claims made concerning the advantages of asynchronous logic are that circuits can take advantage of average case (data dependent) speed rather than worst case speed. Whilst this argument can easily be sustained for a single logic stage its extension to systems consisting of many logic stages has not been widely investigated. This paper reports on investigations into the throughput of asynchronous and synchronous pipelines consisting of alternate latches and logic stages where the data dependent delay is a two valued random variable. The extent to which an average case speed of a single stage which is lower than worst case can be translated into higher throughput in an asynchronous pipeline as compared to a synchronous pipeline is found to be restricted by the coefficient of variation of the distribution of data dependent delay, the length of the pipeline, the number of latches used between each logic stage and the number data items in a loop.