A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition

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Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi, "A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition," Asia and South Pacific Design Automation Conference, pp. 291, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.760016, author = {Kai Zhang and Tsuyoshi Shinogi and Haruhiko Takase and Terumine Hayashi}, title = {A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {291}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.760016}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition SN - 0-7803-5012-X SP EP A1 - Kai Zhang, A1 - Tsuyoshi Shinogi, A1 - Haruhiko Takase, A1 - Terumine Hayashi, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Kai Zhang, Mie University

Tsuyoshi Shinogi, Mie University

Haruhiko Takase, Mie University

Terumine Hayashi, Mie University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.760016

This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates.

Citation:

Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi, "A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition," asp-dac, pp.291, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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