Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner into that of an output device such as the printer, is important for multimedia applications. In this paper, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm proposed in [1] to meet the speed requirement of time-critical applications. To prompt the performance, the presented architecture is dynamically pipelined with unfixed latencies (or data initiation intervals), then the problem of impossible pipelining (and then slow executing) the fuzzy color correction algorithm due to the variable execution length of each iteration in it is solved completely. As a result, a significant (about 2 times) speed-up of the dynamic pipeline architecture with a slight hardware overhead relative to the sequential architecture has been achieved.