Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach

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Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Hidehisa Nagano, Takayuki Suyama, Akira Nagoya, "Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach," Asia and South Pacific Design Automation Conference, pp. 161, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759985, author = {Hidehisa Nagano and Takayuki Suyama and Akira Nagoya}, title = {Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {161}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759985}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach SN - 0-7803-5012-X SP EP A1 - Hidehisa Nagano, A1 - Takayuki Suyama, A1 - Akira Nagoya, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Hidehisa Nagano, NTT Communication Science Laboratories, Japan

Takayuki Suyama, NTT Communication Science Laboratories, Japan

Akira Nagoya, NTT Communication Science Laboratories, Japan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759985

This paper presents an approach to performing applications using reconfigurable computing (RC). Our RC approach is achieved by effective use of design automation systems. Logic circuits specialized for each individual application task are automatically implemented on FPGAs. Such circuits can quickly perform tasks that are time-consuming for general purpose computers. Decoding of binary linear block codes for the evaluation is taken up as an example application. Experimental results show that the time for decoding of the code specific decoding circuit implemented on FPGAs, in which computations are executed in parallel, is much shorter than that of the software decoder.

Citation:

Hidehisa Nagano, Takayuki Suyama, Akira Nagoya, "Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach," asp-dac, pp.161, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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