In SRAM-based FPGA, MOS transistors connect wire segments to construct interconnections between CLBs, resulting in large and unpredictable path delays. So it is necessary to be able to estimate interconnection delays quickly and accurately in order that performance-driven layout and analysis algorithms can achieve high quality. Because the effictive channel resistance of a MOS transistor changes with the voltage on transistor's source pole, general methods for wire nets' path delay estimation, in which wire resistance is always a fixed value, will never be applicable, while SPICE would be too computationally expensive to be used in layout optimization. In this paper, an analytical delay model of FPGA interconnection under ramp input is put forward, and closed-form formulas for delay estimation are proposed. Compared with SPICE, our algorithm has been proved to be fast and accurate enough.