Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)
A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications
Wanchai, Hong Kong
January 18-January 21
ISBN: 0-7803-5012-X
Kang-Jin Lee, Hyundai Electronics Industries Co., Ltd., Ichon, Korea
This paper describes a 10b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 um CMOS show less than ±0.6 LSB and ±2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz.
Citation:
Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon, "A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications," asp-dac, pp.29, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999
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