An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Ju-Hyung Kim Articles by Sung-Wook Hwang Articles by Seung-Hoon Lee Articles by Yong Jee

Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee, "An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications," Asia and South Pacific Design Automation Conference, pp. 25, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759701, author = {Ju-Hyung Kim and Sung-Wook Hwang and Seung-Hoon Lee and Yong Jee}, title = {An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {25}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759701}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications SN - 0-7803-5012-X SP EP A1 - Ju-Hyung Kim, A1 - Sung-Wook Hwang, A1 - Seung-Hoon Lee, A1 - Yong Jee, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Ju-Hyung Kim, Sogang University, Seoul, Korea

Sung-Wook Hwang, Hyundai Electronics Industries Co., Ltd., Ichon, Korea

Seung-Hoon Lee, Sogang University, Seoul, Korea

Yong Jee, Sogang University, Seoul, Korea

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759701

This paper describes an 8b 52MHz CMOS subranging analog-to-digital converter for Integrated Services Digital Network applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's for an increased throughput rate. The fabricated and measured prototype ADC in a 0.8um CMOS process shows nonlinearities less than ±0.4 LSB at an 8b level with 5V and 230mW.

Citation:

Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee, "An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications," asp-dac, pp.25, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.