Relaxed Simulated Tempering for VLSI Floorplan Designs

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Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99)

Wanchai, Hong Kong

January 18-January 21

ISBN: 0-7803-5012-X

	ASCII Text	x
	Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong, "Relaxed Simulated Tempering for VLSI Floorplan Designs," Asia and South Pacific Design Automation Conference, pp. 13, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759698, author = {Jason Cong and Tianming Kong and Dongmin Xu and Faming Liang and Jun S. Liu and Wing Hung Wong}, title = {Relaxed Simulated Tempering for VLSI Floorplan Designs}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {13}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759698}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - Relaxed Simulated Tempering for VLSI Floorplan Designs SN - 0-7803-5012-X SP EP A1 - Jason Cong, A1 - Tianming Kong, A1 - Dongmin Xu, A1 - Faming Liang, A1 - Jun S. Liu, A1 - Wing Hung Wong, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Jason Cong, University of California, Los Angeles

Tianming Kong, University of California, Los Angeles

Dongmin Xu, University of California, Los Angeles

Faming Liang, University of California, Los Angeles

Jun S. Liu, University of California, Los Angeles

Wing Hung Wong, University of California, Los Angeles

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759698

In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy landscape with many local minima separated by high energy barriers. In this paper, we have successfully applied a version of relaxed simulated tempering to slicing floorplan design with consideration of both area and wirelength optimization. Good experimental results were obtained.

Citation:

Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong, "Relaxed Simulated Tempering for VLSI Floorplan Designs," asp-dac, pp.13, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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