Efficient On-Chip Communications for Data-Flow IPs

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	Similar Articles Articles by Antoine Fraboulet Articles by Tanguy Risset

15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04)

Galveston, Texas

September 27-September 29

ISBN: 0-7695-2226-2

	ASCII Text	x
	Antoine Fraboulet, Tanguy Risset, "Efficient On-Chip Communications for Data-Flow IPs," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 293-303, 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04), 2004.

	BibTex	x
	@article{ 10.1109/ASAP.2004.10036, author = {Antoine Fraboulet and Tanguy Risset}, title = {Efficient On-Chip Communications for Data-Flow IPs}, journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on}, volume = {0}, year = {2004}, issn = {1063-6862}, pages = {293-303}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2004.10036}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on TI - Efficient On-Chip Communications for Data-Flow IPs SN - 1063-6862 SP293 EP303 A1 - Antoine Fraboulet, A1 - Tanguy Risset, PY - 2004 KW - system on chip KW - SoC simulation KW - High level synthesis KW - interface generation VL - 0 JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on ER -

Antoine Fraboulet, Citi, Insa-Lyon, France

Tanguy Risset, Inria, Lip, ENS-Lyon, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2004.10036

We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP.

Index Terms:

system on chip, SoC simulation, High level synthesis, interface generation

Citation:

Antoine Fraboulet, Tanguy Risset, "Efficient On-Chip Communications for Data-Flow IPs," asap, pp.293-303, 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'04), 2004

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