In order to address the challenge of providing quality of service guarantees in today's network processing systems, the use efficient scheduling algorithms is required. The efficiency of a scheduler is determined by several factors including its fairness, capability to operate at high speeds, as well as the resources required for its implementation. This paper presents an architecture to support Fair Scheduling (Gigabit FS) considering variable length packets (i.e for packet forwarding/switching networks) over gigabit links. This high speed scheduler is designed to manage 32k flows based on an algorithm that yield efficient implementation in hardware by avoiding the complexity of computing system virtual time function that many Packet F. Queuing (PFQ) algorithm have proposed. Further, we demonstrate the critical factors in designing an effective scheduling engine at gigabit rates and we present several enhancements together with their associated coast.