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14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform
The Hague, The Netherlands
June 24-June 26
ISBN: 0-7695-1992-X
Ayman M. El-Khashab, The University of Texas at Austin
Earl E. Swartzlander, Jr., The University of Texas at Austin
This paper presents a radix-4 modular pipeline architecture for computing the discrete Fourier transform (DFT). For an N-point DFT, two conventional pipeline \sqrt N -point fast Fourier transform (FFT) modules are joined by a specialized center element. The center element contains memories, coefficient ROMs, multipliers, and control logic. Compared with a standard \sqrt N-point pipeline FFT, the modular FFT significantly reduces the number of delay lines to 2\sqrt N. Further, the coeffient storage is concentrated within the center element, thereby reducing the ROM requirement within the pipeline FFT modules. The centralized memory and address generator provide data storage and reordering. The architecture has been analyzed through simulation and compared to the conventional pipeline FFT. The throughput of a standard radix-4 pipeline FFT is maintained with a slightly higher end-to-end latency. A reduction in power is achieved because the modular pipeline exhibits \sqrt N bit transitions on each clock as compared to \frac{N}{2} bit transitions in the conventional pipeline.
Citation:
Ayman M. El-Khashab, Earl E. Swartzlander, Jr., "An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform," asap, pp.378, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003
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