14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03)
A Family of Parallel-Pre.x Modulo 2n - 1 Adders
The Hague, The Netherlands
June 24-June 26
ISBN: 0-7695-1992-X
G. Dimitrakopoulos, Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
H. T. Vergos, Computer Technology Institute, 3 Kolokotroni Str., 26221 Patras, Greece Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
D. Nikolos, Computer Technology Institute, 3 Kolokotroni Str., 26221 Patras, Greece Computer Engineering and Informatics Dept., University of Patras, 26500 Patras, Greece
C. Efstathiou, Informatics Dept., TEI of Athens, 12210 Egaleo, Athens, Greece.
In this paper we at .rst reveal the cyclic nature of idempotency in the case of modulo 2n - 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n- 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.
Citation:
G. Dimitrakopoulos, H. T. Vergos, D. Nikolos, C. Efstathiou, "A Family of Parallel-Pre.x Modulo 2n - 1 Adders," asap, pp.326, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003
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