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1996 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'96) Chicago, IL August 19-August 23 ISBN: 0-8186-7542-X Table of Contents
K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
H.N. Kim, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA pp. 3
V.E. Taylor, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
J. Chen, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
T. Canfield, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
R. Stevens, Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA pp. 12
Jeffrey D. Hirschberg, hirsch@cse.ucsc.edu
Richard Hughey, rph@cse.ucsc.edu
Kevin Karplus, karplus@cse.ucsc.edu
Don Speck, University of California, Santa Cruz, CA 95064 pp. 25
H. Lim, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
C. Yim, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr., Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA pp. 35
J.-C. Bajard, Univ. de Provence, Marseille, France
L.-S. Didier, Univ. de Provence, Marseille, France
J.-M. Muller, Univ. de Provence, Marseille, France pp. 45
J. Villalba, Dept. Comput. Archit., Malaga Univ., Spain
J.C. Arrabal, Dept. Comput. Archit., Malaga Univ., Spain
E.L. Zapata, Dept. Comput. Archit., Malaga Univ., Spain
E. Antelo, Dept. Comput. Archit., Malaga Univ., Spain
J.D. Bruguera, Dept. Comput. Archit., Malaga Univ., Spain pp. 55
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline (Abstract)
K.P. Acken, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
A.K. Garga, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA pp. 65
L. Song, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA pp. 72 Plenary Session
High Performance Multimedia Signal Processing - Is There a Future for DSP?
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation (Abstract)
pp. 83
David A. Parker, Department of Electrical Engineering University of Minnesota
Keshab K. Parhi, Department of Electrical Engineering University of Minnesota pp. 93 pp. 112
A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation (Abstract)
H. Yeo, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Y.H. Hu, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA pp. 122
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources (Abstract)
Jurgen Teich, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Lothar Thiele, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland
Li Zhang, Institute TIK ETH Zurich, Gloriastrasse 35 CH-8092 Zurich, Switzerland pp. 131 pp. 145
Automatic Generation of Modular Mappings (Abstract)
Hyuk-Jae Lee, Purdue University {hyuk,fortes}@ecn.purdue.edu
Jose A.B. Fortes, Purdue University {hyuk,fortes}@ecn.purdue.edu pp. 155
M. Boo, Univ. Santiago de Compostela elmboo@usc.es
F. Arguello, Univ. Santiago de Compostela elmboo@usc.es
J.D. Bruguera, Univ. Santiago de Compostela elmboo@usc.es
E.L. Zapata, Univ. Santiago de Compostela elmboo@usc.es pp. 165
pp. 175
S. Peng, Aizu Univ., Fukushima, Japan
S. Sedukhin, Aizu Univ., Fukushima, Japan
I. Sedukhin, Aizu Univ., Fukushima, Japan pp. 183
A Common Architecture For The DWT and IDWT (Abstract)
M. Vishwanath, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
R.M. Owens, Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA pp. 193
G. Even, Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany
A. Litman, Fachbereich Inf., Saarlandes Univ., Saarbrucken, Germany pp. 199 pp. 209
M.I. Patel, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA pp. 221
A. Wang, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
K. Yao, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
R.E. Hudson, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
D. Korompis, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
F. Lorenzelli, Electrical Engineering Dept. UCLA, Los Angeles, CA 90095-1594
S. Soli, House Ear Institute Los Angeles,CA 90057
S. Gao, House Ear Institute Los Angeles,CA 90057 pp. 231
Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems (Abstract)
David R. Surma, University of Notre Dame
Edwin Hsing-Mean Sha, University of Notre Dame pp. 240
Daping Song, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Thierry Divoux, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France
Francis LePage, Centre de Recherche en Automatique de Nancy Universite de Nancy I, BP239, 54506 Vandoeuvre-les-Nancy cedex, France pp. 250
High Speed Networks
K.M. Fant, Theseus Logic Inc., St. Paul, MN, USA
S.A. Brandt, Theseus Logic Inc., St. Paul, MN, USA pp. 261
R.W. Hartenstein, Kaiserslautern Univ., Germany
J. Becker, Kaiserslautern Univ., Germany
M. Herz, Kaiserslautern Univ., Germany
R. Kress, Kaiserslautern Univ., Germany
U. Nageldinger, Kaiserslautern Univ., Germany pp. 274
D.R. Smith, Dept. of Comput. Sci., State Univ. of New York, Stony Brook, NY, USA pp. 284
B.K. Fawcett, Xilinx Inc., San Jose, CA, USA
J. Watson, Xilinx Inc., San Jose, CA, USA pp. 293
Naren Narasimhan, University of Cincinnati
Vinoo Srinivasan, University of Cincinnati
Madhavi Vootukuru, University of Cincinnati
Jeff Walrath, University of Cincinnati
Sriram Govindarajan, University of Cincinnati
Ranga Vemuri, University of Cincinnati pp. 303 pp. 313
Jacobi-Specific Processor Arrays (Abstract)
H.W. Van Dijk, Philips Components, Eindhoven, Netherlands
G.J. Hekstra, Philips Components, Eindhoven, Netherlands
E.F. Deprettere, Philips Components, Eindhoven, Netherlands pp. 323
A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation (Abstract)
pp. 342 pp. 353
S. S. Bhattacharyya, Semiconductor Research Laboratory, Hitachi America, Ltd. shuvra@halsrl.com
S. Sriram, DSP R&D Center, Texas Instruments Incorporated sriram@hc.ti.com
E. A. Lee, University of California at Berkeley eal@eecs.berkeley.edu, fax: (510)642-2739. pp. 365
F. de Dinechin, IRISA, Rennes, France
S. Robert, IRISA, Rennes, France pp. 381
pp. 391
Edin Hodzic, HaL Computer Systems ehodzic@scu.edu
Weijia Shang, Santa Clara University wshang@scus19.scu.edu pp. 402 pp. 415 Usage of this product signifies your acceptance of the Terms of Use.
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