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1995 IEEE International Conference on Application-Specific Array Processors (ASAP'95)
Strasbourg, France
July 24-July 26
ISBN: 0-8186-7109-2
Table of Contents
Opening Session, Chair: P. Cappello
Keynote Address: Array Processing in Embedded Systems
Session 1: Scheduling and Mapping, Chair: J. Teich
D. Wilde, Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
S. Rajopadhye, Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
pp. 1
Alain Darte, Ecole Normale Sup_rieure de Lyon
Fredric Vivien, Ecole Normale Sup_rieure de Lyon
pp. 13
Chris Scheiman, University of California Santa Barbara
Peter Cappello, University of California Santa Barbara
pp. 26
Hyuk-Jae Lee, Purdue University, W. Lafayette, IN 47907
Jose A.B. Fortes, Purdue University, W. Lafayette, IN 47907
pp. 34
Session 2: Architectures I, Chair: C. Mongenet
V. Bokka, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
H. Gurla, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
S. Olariu, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
J.L. Schwing, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
L. Wilson, Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
pp. 42
Anders Kugler, Swiss Federal Institute of Technology
Roger-David Hersch, Swiss Federal Institute of Technology
pp. 76
Session 3: Arithmetic I, Chair: R. Owens
Luca Breveglieri, Politecnico di Milano
Luigi Dadda, Politecnico di Milano
Vincenzo Piuri, Politecnico di Milano
pp. 93
Michael J. Schulte, The University of Texas at Austin
Earl E. Swartzlander, Jr., The University of Texas at Austin
pp. 104
Rong Lin, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
S. Olariu, Dept. of Comput. Sci., State Univ. of New York, Genesco, NY, USA
pp. 113
Session 4: Poster Presentations, Chair: R. Owens
Parallel Digital Elevation Model Algorithm
R.S. Bajwa, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 121
B. Saha, Dept. of Electr. Eng., Binghamton Univ., NY, USA
J.S. Mertoguno, Dept. of Electr. Eng., Binghamton Univ., NY, USA
N.G. Bourbakis, Dept. of Electr. Eng., Binghamton Univ., NY, USA
pp. 125
Reiner W. Hartenstein, University of Kaiserslautern
Jrgen Becker, University of Kaiserslautern
Rainer Kress, University of Kaiserslautern
Helmut Reinig, University of Kaiserslautern
Karin Schmidt, University of Kaiserslautern
pp. 129
Invited Talk, Chair: S.Y. Kung
Real-Time Image Processing for Multimedia Applications at Matra-Hachette
Session 5: Signal and Image Processing, Chair: S. Y. Kung
Session 6: Motion Estimation, Chair: P. Quinton
P. Baglietto, DIST - University of Genoa
M. Maresca, DIST - University of Genoa
A. Migliaro, DIST - University of Genoa
M. Migliardi, DIST - University of Genoa
pp. 182
Heung-Nam Kim, The Pennsylvania State University
Mary Jane Irwin, The Pennsylvania State University
Robert Michael Owens, The Pennsylvania State University
pp. 204
Invited Talk, Chair: J.M. Muller
Computer Arithmetic: Exploiting Redundancy in Number Representations
Session 7: Architecture II, Chair: J.M. Muller
Zhan Chen, University of Massachusetts
Israel Koren, University of Massachusetts
pp. 222
Session 8: Arithmetic II, Chair: E.E. Swartzlander
Roberto R. Osorio, University of Santiago de Compostela
Elisardo Antelo, University of Santiago de Compostela
Javier D. Bruguera, University of Santiago de Compostela
Javier D. Bruguera, University of Santiago de Compostela
Julio Villalba, University of Malaga
Emilio L. Zapata, University of Malaga
pp. 246
J. Villalba, University of Malaga, SPAIN
J.A. Hidalgo, University of Malaga, SPAIN
E.L. Zapata, University of Malaga, SPAIN
E. Antelo, University of Santiago de Compostela, SPAIN
J.D. Bruguera, University of Santiago de Compostela, SPAIN
pp. 258
W. Luo, VLSI Res. Group, Windsor Univ., Ont., Canada
G.A. Jullien, VLSI Res. Group, Windsor Univ., Ont., Canada
N.M. Wigley, VLSI Res. Group, Windsor Univ., Ont., Canada
W.C. Miller, VLSI Res. Group, Windsor Univ., Ont., Canada
Z. Wang, VLSI Res. Group, Windsor Univ., Ont., Canada
pp. 270
V.P. Markova, Computing Center, Siberian Div. of the Russian Academy of Sciences
pp. 290
Session 9: Design Methodologies, Chair: J. Fortes
Shuvra S. Bhattacharyya, Hitachi America Ltd.
Sundararajan Sriram, University of California, Berkeley California, 94720
Edward A. Lee, University of California, Berkeley California, 94720
pp. 298
Pierre-Yves Calland, Ecole Nationale Superieure de Lyon
Tanguy Risset, IRISA, Campus de Beaulieu
pp. 330
Closing Session and Best Paper Award, Chair: J. Fortes
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