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16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03)
Hardware Implementations of Denormalized Numbers
Santiago de Compostela, Spain
June 15-June 18
ISBN: 0-7695-1894-X
Eric M. Schwarz, IBM Server Division
Martin Schmookler, IBM Server Division
Son Dao Trong, IBM Server Division
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than in harware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. This paper will summarize the little known techniques for handling denormalized numbers. Most of the techniques discussed have only been discussed in filed or pending patent applications.
Citation:
Eric M. Schwarz, Martin Schmookler, Son Dao Trong, "Hardware Implementations of Denormalized Numbers," arith, pp.70, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003
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