Foreword

Committees (PDF)

pp. x

Additional Reviewers (PDF)

pp. xii

Keynote Speech

Computer Arithmetic-A Processor Architect's Perspective (PDF)

Ruby B. Lee

pp. 0003

Session 1: Binary Strings in Computer Arithmetic

Leading Zero Anticipation and Detection?A Comparison of Methods (Abstract)

Martin S. Schmookler, IBM Server Development

Kevin J. Nowka, IBM Austin Research Laboratory

pp. 0007

PDF

Bounds on Runs of Zeros and Ones for Algebraic Functions (Abstract)

Tomas Lang, University of California at Irvine

Jean-Michel Muller, Ecole Normale Superieure de Lyon

pp. 0013

PDF

Session 2: Multiplication and Exponentiation

Binary Multiplication Radix-32 and Radix-256 (Abstract)

Peter-Michael Seidel, Southern Methodist University

Lee D McFearin, Southern Methodist University

David W Matula, Southern Methodist University

pp. 0023

PDF

Analysis of Column Compression Multipliers (Abstract)

K'Andrea C. Bickerstaff, University of Texas at Austin

Earl E. Swartzlander Jr, University of Texas at Austin

Michael J. Schulte, Lehigh University

pp. 0033

PDF

Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree (Abstract)

J.A. Piñeiro, University Santiago de Compostela

J.D. Bruguera, University Santiago de Compostela

J.M. Muller, Ecole Normale Superieure de Lyon

pp. 0040

PDF

Session 3: Cryptography

Modular Multiplication and Base Extensions in Residue Number Systems (Abstract)

Jean-Claude Bajard, LIRMM

Laurent-Stephane Didier, Universite de Bretagne Occidentale

Peter Kornerup, SDU/Odense University

pp. 0059

PDF

Efficient Computation of Multiplicative Inverses for Cryptographic Applications (Abstract)

M. A. Hasan, University of Waterloo

pp. 0066

PDF

Optimised Squaring of Long Integers Using Precomputed Partial Products (Abstract)

Braden Phillips, Cardiff University

pp. 0073

PDF

Session 4: Division and Square Root

Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation (Abstract)

Tomas Lang, University of California at Irvine

Elisardo Antelo, University of Santiago

pp. 0083

PDF

A Hardware Algorithm for Computing Reciprocal Square Root (Abstract)

Naofumi Takagi, Nagoya University

pp. 0094

PDF

Improved Table Lookup Algorithms for Postscaled Division (Abstract)

David W. Matula, Southern Methodist University

pp. 0101

PDF

Session 5: Elementary Functions and Rounding

Worst Cases for Correct Rounding of the Elementary Functions in Double Precision (Abstract)

Vincent Lefévre, INRIA, Projet Spaces, LORIA, Campus Scientifique

Jean-Michel Muller, Ecole Normale Superieure de Lyon

pp. 0111

PDF

Generation and Analysis of Hard to Round Cases for Binary Floating Point Division (Abstract)

Lee D. McFearin, Southern Methodist University

David W. Matula, Southern Methodist University

pp. 0119

PDF

Some Improvements on Multipartite Table Methods (Abstract)

Florent de Dinechin, Ecole Normale Superieure de Lyon-INRIA

Arnaud Tisserand, Ecole Normale Superieure de Lyon-INRIA

pp. 0128

PDF

High-Performance Architectures for Elementary Function Generation (Abstract)

Jun Cao, San Jose State University

Belle W.Y. Wei, San Jose State University

Jie Cheng, San Jose State University

pp. 0136

PDF

Session 6: Number Systems

A Decimal Floating-Point Specification (Abstract)

Michael F. Cowlishaw, IBM UK

Eric M. Schwarz, IBM Server Division

Ronald M. Smith, IBM Server Division

Charles F. Webb, IBM Server Division

pp. 0147

PDF

Algorithms for Quad-Double Precision Floating Point Arithmetic (Abstract)

Yozo Hida, University of California, Berkley

Xiaoye S. Li, NERSC: Lawrence Berkeley National Laboratory

David H. Bailey, NERSC: Lawrence Berkeley National Laboratory

pp. 0155

PDF

Effective Continued Fractions (Abstract)

David Lester, Manchester University

pp. 0163

PDF

Session 7: Floating Point Units

1-GHz HAL SPARC64? Dual Floating Point Unit with RAS Features (Abstract)

Ajay Naini, HAL Computer Systems

Atul Dhablania, HAL Computer Systems

Warren James, HAL Computer Systems

Debjit Das Sarma, HAL Computer Systems

pp. 0173

PDF

On the Design of Fast IEEE Floating-Point Adders (Abstract)

Peter-Michael Seidel, Southern Methodist University

Guy Even, Tel-Aviv University

pp. 0184

PDF

In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32 (Abstract)

Cheol-Ho Jeong, Yonsei University

Woo-Chan Park, Yonsei University

Tack-Don Han, Yonsei University

Moon-Key Lee, Yonsei University

Sang-Woo Kim, Samsung Electronics Co.

pp. 0195

PDF

Session 8: Addition

Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition (Abstract)

Javier D. Bruguera, University of Santiago de Compostela

Tomas Lang, University of California at Irvine

pp. 0203

PDF

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands (Abstract)

H.T. Vergos, University of Patras

D. Nikolos, University of Patras

C. Efstathiou, TEI of Athens

pp. 0211

PDF

Parallel Prefix Adder Design (Abstract)

Andrew Beaumont-Smith, The University of Adelaide

Cheng-Chew Lim, The University of Adelaide

pp. 0218

PDF

Session 9: Logarithmic Number Systems

Low-Power Properties of the Logarithmic Number System (Abstract)

V. Paliouras, University of Patras

T. Stouraitis, University of Patras

pp. 0229

PDF

Unrestricted Faithful Rounding is Good Enough for Some LNS Applications (Abstract)

Mark G. Arnold, UMIST

Colin Walter, UMIST

pp. 0237

PDF

The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications (Abstract)

V. S. Dimitrov, University of Windsor

J. Eskritt, University of Windsor

L. Imbert, University of Windsor

G. A. Jullien, University of Windsor

W.C. Miller, University of Windsor

pp. 0247

PDF

Session 10: On-Line Arithmetic

On-line Arithmetic for Detection in Digital Communication Receivers (Abstract)

Sridhar Rajagopal, Rice University

Joseph R. Cavallaro, Rice University

pp. 0257

PDF

A Design of Radix-2 On-line Division Using LSA Organization (Abstract)

Alexandre F. Tenca, Oregon State University

Syed Ubaid Hussaini, University of Applied Sciences, Offenburg, Germany

pp. 0266

PDF

Addendum: Reprinted Paper from the 14th Computer Arithmetic Symposium

A Family of Adders (Abstract)

Simon Knowles, Aztec Centre

pp. 0277

PDF