Abstract: The double-datapath organization of a floating-point adder results in a reduced latency. One of the main characteristics of this organization is the combination of the addition/subtraction with the rounding into a single Add/Round module, which is implemented as one pipeline stage and might be responsible for the cycle time. We propose the utilization of the most-significant carry detector and the corresponding adder using the reverse-carry approach to reduce the latency of this Add/Round module. In addition, the particular organization of the reverse-carry adder is used to reduce the contribution on the delay of the row of half adders that is included in the FAR datapath to produce the sum plus two. Estimates for a 64-bit Add/Round module show a potential reduction of delay of about 15%.