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15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01)
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32
Vail, Colorado
June 11-June 13
ISBN: 0-7695-1150-3
Cheol-Ho Jeong, Yonsei University
Woo-Chan Park, Yonsei University
Tack-Don Han, Yonsei University
Moon-Key Lee, Yonsei University
Sang-Woo Kim, Samsung Electronics Co.
Abstract: The CalmRISC32 FPU (Floating-Point Unit) is a RISC coprocessor for embedded system applications. It supports IEEE-754 standard single precision floating-point addition, floating-point subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, load, store, etc. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order, if such constraints as data dependency, resource conflict, and exception prediction are resolved. Standard cell-base design techniques were used to reduce design time and expense. The first prototype operated at approximately 70MHz with the worst-case delay in gate level simulation.
Citation:
Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon-Key Lee, Sang-Woo Kim, "In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32," arith, pp.0195, 15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01), 2001
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