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15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01)
A Hardware Algorithm for Computing Reciprocal Square Root
Vail, Colorado
June 11-June 13
ISBN: 0-7695-1150-3
ASCII Text
x 
 
Naofumi Takagi, "A Hardware Algorithm for Computing Reciprocal Square Root," Computer Arithmetic, IEEE Symposium on, pp. 0094, 15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01), 2001.
 
 
BibTex
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@article{ 10.1109/ARITH.2001.930108,
author = {Naofumi Takagi},
title = {A Hardware Algorithm for Computing Reciprocal Square Root},
journal ={Computer Arithmetic, IEEE Symposium on},
volume = {0},
year = {2001},
isbn = {0-7695-1150-3},
pages = {0094},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2001.930108},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer Arithmetic, IEEE Symposium on
TI - A Hardware Algorithm for Computing Reciprocal Square Root
SN - 0-7695-1150-3
SP
EP
A1 - Naofumi Takagi,
PY - 2001
VL - 0
JA - Computer Arithmetic, IEEE Symposium on
ER -
 
Naofumi Takagi, Nagoya University
Abstract: A hardware algorithm for computing the reciprocal square root which appears frequently in multimedia and graphics applications is proposed. The reciprocal square root is computed by iteration of carry-propagation-free additions, shifts, and multiplications by one digit. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the digit set, and etc. Each version of the algorithm can be implemented as a sequential (folded) circuit or a combinational (unfolded) circuit, which has a regular array structure suitable for VLSI.
Citation:
Naofumi Takagi, "A Hardware Algorithm for Computing Reciprocal Square Root," arith, pp.0094, 15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01), 2001
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