We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient- digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix 2^k and n-bit precision are obtained in terms of full- adder delays. The speedup with respect to radix 2 is greater than 3.3 for k>5 and n>63. The cost increases as a function of the radix. For the case r=64 and n=64, the increase in area with respect to r=2 is about 6.6 times plus a 512x10-bit table. The proposed scheme has been designed and verified using VHDL and a 1.2um CMOS standard gate technology from MOSIS library.