The paper presents the foundations for a packet forwarding floating point format and the design of a rounder ensuring compatibility between packet forwarding format and the standard binary IEEE 754 floating point format. The packet forwarding format and related addition and multiplication algorithms described in this series propose a new ALU pipeline paradigm for handling data hazards in pipelined floating point operations. The execution phases for the adder and multiplier packet forwarding pipelines are illustrated by a proposed implementation having four stages. The latter two stages in each pipeline employ the rounder described herein. The stages of the execution phase are intended to map to logic designs, with only some fifteen logic levels per stage allowing stages to be mapped to reasonably short cycles. The packet forwarding format provides for input and output in packet format with only two cycle effective latency between cooperating adder and multiplier pipelines. The designs we propose cut the effective latency in half and reduce the stall cycles by a factor of three compared to conventional forwarding pipelines processing data dependent operations. The speedup is realized, with preservation of IEEE 754 binary floating point compatibility.