loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
13th IEEE Symposium on Computer Arithmetic (ARITH-13 '97)
A GaAs 32-bit Adder
Asilomar, CA
March 06-March 09
ISBN: 0-8186-7846-1
Andrew Beaumont-Smith, The University of Adelaide
Neil Burgess, The University of Adelaide
This paper presents a new parallel GaAs 32-bit adder based on a combination of the Han-Carlson and Kowalczuk parallel adders. GaAs is particularly sensitive to loading so our aim was to reduce the wire lengths and the fan-out of each gate. Our architecture achieves this by significantly reducing the number of cells in the carry tree while not significantly reducing its speed. The delay of the adder fabricated in 0.6mm MESFET GaAs technology was measured at 1.27ns with a power dissipation of 114mW at 0.9V. The area is 0.3mm2 with a maximum density of 8000 transistors/mm2. The figure of merit is 0.21mW/MHz.gate.
Index Terms:
Gallium Arsenide, GaAs, adder, VLSI, high speed adder, low power
Citation:
Andrew Beaumont-Smith, Neil Burgess, "A GaAs 32-bit Adder," arith, pp.10, 13th IEEE Symposium on Computer Arithmetic (ARITH-13 '97), 1997
Usage of this product signifies your acceptance of the Terms of Use.