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12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95)
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm
Bath, England
July 19-July 21
ISBN: 0-8186-7089-4
Feng Zhou, Odense University
Peter Kornerup, Odense University
This paper describes DCT (IDCT) computations using the CORDIC algorithm. By rewriting the DCT, for a 1*8 DCT only 6 CORDIC computations are needed, whereas a 1*16 DCT requires 22 CORDIC computations. But these can all be pipelined through a single CORDIC unit, so 16*16 DCT's becomes feasible for HDTV compression. Only some simple adders, registers and a more complicated carry look-ahead adder are needed, and the computing speed can be very high. Limited only by the delay of a carry look-ahead adder, the delay time of the pipelined structure is 2-10ns and the data rate is 100-500MHz for an 8*8 DCT/IDCT and 72.2-366.6MHz for a 16*16 DCT/IDCT when using two units.
Citation:
Feng Zhou, Peter Kornerup, "High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm," arith, pp.180, 12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95), 1995
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