A GaAs IEEE Floating Point Standard Single Precision Multiplier

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	Similar Articles Articles by S. Cui Articles by N. Burgess Articles by M. Liebelt Articles by K. Eshraghian

12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95)

Bath, England

July 19-July 21

ISBN: 0-8186-7089-4

	ASCII Text	x
	S. Cui, N. Burgess, M. Liebelt, K. Eshraghian, "A GaAs IEEE Floating Point Standard Single Precision Multiplier," Computer Arithmetic, IEEE Symposium on, pp. 91, 12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95), 1995.

	BibTex	x
	@article{ 10.1109/ARITH.1995.465372, author = {S. Cui and N. Burgess and M. Liebelt and K. Eshraghian}, title = {A GaAs IEEE Floating Point Standard Single Precision Multiplier}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {1995}, issn = {1063-6889}, pages = {91}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.1995.465372}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - A GaAs IEEE Floating Point Standard Single Precision Multiplier SN - 1063-6889 SP EP A1 - S. Cui, A1 - N. Burgess, A1 - M. Liebelt, A1 - K. Eshraghian, PY - 1995 KW - floating point multiplier KW - rounding algorithm KW - modified carry save array KW - GaAs technology VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER -

S. Cui, Univ. of Adelaide

N. Burgess, Univ. of Adelaide

M. Liebelt, Univ. of Adelaide

K. Eshraghian, Univ. of Adelaide

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.1995.465372

This paper presents a GaAs IEEE floating point standard single precision multiplier. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and the compact layout style achieves 4ns multiplication time with 3.5W power dissipation at 75oC giving 14mW/MHz. The area is 2.43mm by 3.77mm (excluding pads) and uses 28,000 transistors to give a density of 3056 transistors/mm2 for 0.8-um GaAs technology.

Index Terms:

floating point multiplier, rounding algorithm, modified carry save array, GaAs technology

Citation:

S. Cui, N. Burgess, M. Liebelt, K. Eshraghian, "A GaAs IEEE Floating Point Standard Single Precision Multiplier," arith, pp.91, 12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95), 1995

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