12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95)
Application of fast layout synthesis environment to dividers evaluation
Bath, England
July 19-July 21
ISBN: 0-8186-7089-4
A. Houelle, MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
H. Mehrez, MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
N. Vaucher, MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
L. Montalvo, MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
A. Guyot, MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
Experience has shown that generator programs are quite often written by VLSI designers, as they hold the empirical knowledge better than anyone. However, their ability does not necessarily include programming and debugging skills: these designers have to focus on the problem at hand not on the tools or the language they use to solve it. GenOptim has been created to quickly design efficient IEEE 754 floating-point macro-cell generators that do not rely on particular target technologies. Whereas the design of fast and efficient adders, multipliers and shifters is well understood division and square root remain a serious design challenge. GenOptim was used to quickly evaluate new divider architectures.
Index Terms:
dividing circuits; floating point arithmetic; programming environments; layout synthesis environment; dividers evaluation; generator programs; GenOptim; IEEE 754 floating-point macro-cell generators; division; square root
Citation:
A. Houelle, H. Mehrez, N. Vaucher, L. Montalvo, A. Guyot, "Application of fast layout synthesis environment to dividers evaluation," arith, pp.67, 12th IEEE Symposium on Computer Arithmetic (ARITH-12 '95), 1995