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Second International Conference on Application of Concurrency to System Design (ACSD'01)
Analysis of Performance Limitations in Multithreaded Multiprocessor Architectures
Newcastle upon Tyne, UK
June 25-June 29
ISBN: 0-7695-1071-X
W.M. Zuberek, Memorial University of Nfld
The performance of modern multiprocessor systems is increasingly limited by interconnection delays or long latencies of memory subsystems. Instruction-level multithreading is a technique to tolerate such long latencies by switching from one instruction thread to another and continuing instruction execution concurrently with the long-latency operations. Using timed Petri net models, the paper analyzes performance limitations introduces by different components of distributed-memory multithreaded multiprocessor systems. Simulation results are used to compare performance improvements obtained by replicating critical components of the system to those obtained using components with better performance characteristics.
Citation:
W.M. Zuberek, "Analysis of Performance Limitations in Multithreaded Multiprocessor Architectures," acsd, pp.43, Second International Conference on Application of Concurrency to System Design (ACSD'01), 2001
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