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Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
January/February 2005 (vol. 25 no. 1)
pp. 30-40
ASCII Text
x 
 
Thomas H. Dunigan Jr., Jeffrey S. Vetter, James B. White III, Patrick H. Worley, "Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture," IEEE Micro, vol. 25, no. 1, pp. 30-40, January/February, 2005.
 
 
BibTex
x
 
@article{ 10.1109/MM.2005.20,
author = {Thomas H. Dunigan Jr. and Jeffrey S. Vetter and James B. White III and Patrick H. Worley},
title = {Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture},
journal ={IEEE Micro},
volume = {25},
number = {1},
issn = {0272-1732},
year = {2005},
pages = {30-40},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.20},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
IS - 1
SN - 0272-1732
SP30
EP40
EPD - 30-40
A1 - Thomas H. Dunigan Jr.,
A1 - Jeffrey S. Vetter,
A1 - James B. White III,
A1 - Patrick H. Worley,
PY - 2005
VL - 25
JA - IEEE Micro
ER -
 
Thomas H. Dunigan Jr., Oak Ridge National Laboratory
Jeffrey S. Vetter, Oak Ridge National Laboratory
James B. White III, Oak Ridge National Laboratory
Patrick H. Worley, Oak Ridge National Laboratory
The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. Our results show that this high bandwidth and low latency for remote memory accesses translate into improved application performance on important applications.
Citation:
Thomas H. Dunigan Jr., Jeffrey S. Vetter, James B. White III, Patrick H. Worley, "Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture," IEEE Micro, vol. 25, no. 1, pp. 30-40, Jan./Feb. 2005, doi:10.1109/MM.2005.20
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