ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine

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January/February 2004 (vol. 24 no. 1)

pp. 24-31

	ASCII Text	x
	Greg Regnier, Dave Minturn, Gary McAlpine, Vikram A. Saletore, Annie Foong, "ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine," IEEE Micro, vol. 24, no. 1, pp. 24-31, January/February, 2004.

	BibTex	x
	@article{ 10.1109/MM.2004.1268989, author = {Greg Regnier and Dave Minturn and Gary McAlpine and Vikram A. Saletore and Annie Foong}, title = {ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine}, journal ={IEEE Micro}, volume = {24}, number = {1}, issn = {0272-1732}, year = {2004}, pages = {24-31}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.1268989}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine IS - 1 SN - 0272-1732 SP24 EP31 EPD - 24-31 A1 - Greg Regnier, A1 - Dave Minturn, A1 - Gary McAlpine, A1 - Vikram A. Saletore, A1 - Annie Foong, PY - 2004 VL - 24 JA - IEEE Micro ER -

Greg Regnier, Intel

Dave Minturn, Intel

Gary McAlpine, Intel

Vikram A. Saletore, Intel

Annie Foong, Intel

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.1268989

As part of an effort to accelerate server TCP/IP networking, Intel R&D has developed a software prototype that uses one of the intel xeon processors in a multiprocessor server as a packet processing engine (PPE). This prototype serves as a vehicle for empirical measurement and analysis of a highly programmable PPE that is closely tied to the server's core CPU and memory complex.

Citation:

Greg Regnier, Dave Minturn, Gary McAlpine, Vikram A. Saletore, Annie Foong, "ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine," IEEE Micro, vol. 24, no. 1, pp. 24-31, Jan./Feb. 2004, doi:10.1109/MM.2004.1268989

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